A simplified model of the reflow soldering process

Previous models of the reflow soldering process have used commercial finite difference (FD) or computational fluid dynamics simulation software to create detailed representations of the product and/or the reflow furnace. Such models have been shown to be highly accurate at predicting the temperatures a PCB design will achieve during the reflow process. These models are however complex to generate and analysis times are long, even using modern high performance workstations. With the move to adopt lead free soldering technology, and the consequently higher reflow process temperatures, optimisation of the reflow profile is gaining a renewed emphasis. This paper describes a less complex approach to modelling of the process, which uses simplified representations of both the product and the process, together with a FD solver developed specifically for this application, and which achieves an accuracy comparable with more detailed models. In order to establish an accurate representation of the specific reflow furnace being simulated, a reflow logger is used to make measurements of the temperature and level of thermal convection at each point along the length of the furnace for a small number of carefully chosen reflow profiles. The temperatures for any other reflow profile can then be predicted from these measurements

Reflow soldering process simulation: a simplified model

Established models of temperature development during reflow soldering have used general purpose, finite difference (FD) or computational fluid dynamics modelling tools to create detailed representations of both the product and the reflow furnace. Such models have been shown to achieve a high degree of accuracy, but are complex to generate and analysis times are long. With the move to adopt lead free soldering technology, and the consequently higher reflow process temperatures, optimisation of the reflow profile will gain a renewed emphasis. This paper will report a model of the process which uses simplified representations of both the product and the process which achieves an accuracy comparable with more detailed models. In order to establish an accurate representation of the specific reflow furnace being simulated, a reflow logger is used to make measurements of the temperature and level of thermal convection at each point along the length of the furnace for a small number of carefully chosen reflow profiles. The behaviour for any other reflow profile may then be extrapolated from these measurements

Thermal design of high power semiconductor packages for aircraft electronic systems

The More Electric Aircraft is likely to require more extensive use of power electronics, for which thermal management will be a key issue. This paper presents an approach to designing integrated air cooled heatsinks which is being developed by Loughborough University as part of the CARAD funded Variable Frequency to Constant Frequency (VFCF) Converter project in collaboration with project partners TRW Aeronautical Systems, Mitel Semiconductor, AEA Technology and BAe Airbus. The paper shows how simple models of the heat transfer from heatsink fins, which are based on well established empirical correlations, may be utilised in combination with either simple analytical models or two dimensional finite element models of the heat conduction from the semiconductor die through the multilayer package structure to the base of the fins. These models allow the generation of design curves which may be used to rapidly explore a wide range of design options before selecting potential designs for more detailed evaluation using 3D FE analysis. In systems such as a VFCF convertor the semiconductor devices are switched at high frequency to ensure good input and output current waveforms. The power dissipated in the semiconductors, and therefore the heatsink weight, will however increase with the switching frequency, whereas the associated filtering components will be smaller and lighter at higher frequencies. The optimisation of the overall system weight therefore involves a tradeoff between the heatsinking and filtering requirements rather than just determining the optimum heatsink design for a specific power dissipatio

Temperature cycling of surface mounted thick film 'zero-ohm' jumpers

Thermal cycling tests for surface mounted components are usually taken around a mean temperature of approximately 35°C (e.g., -55°C to +125°C; -40°C to +110°C). To test the effect of different maximum temperatures thermal cycling tests using a lower temperature of -55°C have been conducted with alumina/thick film 'zero-ohm' jumper chips with nickel barriers. These are connected in series chains and wave soldered on to FR-4 test coupons (128 chips/coupon). The test regimes used were -55°C to +5°C; +65°C; +95°C, +110°C and +125°C. Resistance changes before and after cycling were observed at room temperature. After 100 cycles changes of approximately +200 mΩ were observed against a total resistance of 5.5 Ω. However, more detailed examination showed that a top temperature of +95°C gives optimum results with a total change over 100 cycles of +4.9%

IGBT package design for high power aircraft electronic systems

This paper will discuss the design of semiconductor packages having integrated air cooled heatsinks for use in high power electronic systems. It will demonstrate how simple models of the heat transfer from the heatsink fins, which are based on empirical correlations, may be utilised in combination with either simple analytical models or two dimensional finite difference (FD) models of the heat conduction from the semiconductor die through the multilayer package structure to the base of the fins. These models allow the rapid evaluation of performance under both steady state and transient overload conditions, and can be used to rapidly explore a wide range of design options before selecting candidate layouts for more detailed evaluation using, for example, 3D FD analysis. Wind tunnel experiments, which will also be reported, have been carried out to verify the modelling results for different semiconductor device layouts. These trials demonstrate excellent agreement between the models and experimental results

The effect of co-planarity variation on anisotropic conductive adhesive assemblies

Anisotropic Conductive Adhesives (ACAs) consist of a polymer adhesive matrix containing fine conductive particles dispersed either randomly, or more rarely in an ordered way. The primary objective of this experimental research was to understand the effects of a non-uniform bond thickness due to non co-planarity of the component or substrate terminations in ACA assemblies. This has been achieved through measurements of the conductivity variations of ACA joints in a number of ACA assemblies, where the component bump plane and substrate plane were deliberately held in different degrees of relative rotation from parallel during adhesive cure. Measurements of the joint resistances versus rotational angle, for a constant bonding force, were made for 10 levels of rotation of the chips relative to the substrates. The results showed that the resistances of the joints in the assemblies exhibited three distinct types of behaviour: stable joint resistances; gradually increasing resistances and unstable resistances. In conclusion, it is shown that ACA joints are very sensitive to the uniformity of the bond thickness, as the larger the rotations were, the lower and less uniform the joint conductivities were, however, the joints were uniform if the rotation angles were controlled within certain limits

Application of adhesives in MEMS and MOEMS assembly: a review

This paper presents a review of the recent literature on the use of adhesives in MEMS packaging applications. The aim of this review has been to establish the current applications of adhesives in MEMS and MOEMS assembly and to investigate the limitations and future requirements of these materials. The review has shown that while there is a wealth of information available on the packaging of MEMS devices, there is very limited detail available within the public domain regarding the specific uses of adhesives and in particular exactly which products are in use. The paper begins with an overview of the uses of adhesives in MEMS packaging, subdivided into sections on structural adhesives, adhesives for optical applications and other applications. The paper then describes methods for adhesive dispensing and issues with adhesive use which affect the reliability of the package. The reliability of MEMS devices assembled using adhesives is a challenging issue, being more than a simple combination of electrical, mechanical and material reliability. Many failure modes in MEMS devices can be attributed to the adhesives used in the assembly; for example, thermal expansion mismatches can cause stress in the die attach, while outgassing from epoxies can cause failure of sealed devices and contamination of optical surfaces

3D study of thermal stresses in lead-free surface mount devices

The paper presents the study of non-uniform temperature distributions in a flip chip electronic assembly, and the use of these temperature distributions to analyse the thermal stresses in lead-free solder joints in surface mount devices. The thermal stresses in the solder joints are mainly due to the mismatch in the coefficients of thermal expansions between the component and substrate materials, and temperature gradient in the electronic assembly. The thermo-elasto-visco-plastic finite element analysis is carried out to investigate the extent of thermal stresses induced in solder joints between a surface mount component and a FR4 circuit board (substrate) under conditions of thermal cycling with the chip resistor operating at its full power condition. Three different cases of spatial temperature distributions are considered including one with an experimentally obtained non-uniform temperature distribution. A comparative study of thermal stresses is performed using a near-eutectic SnAgCu solder material for three different thermal cases

The penetration limit of poly(4-vinyl phenol) thin films for etching via holes by inkjet printing

This paper reports the penetration limit of via holes through dissolving dielectric polymer thin films by inkjet printing. It was found that both the outer diameter of via holes and the polymer thickness affect the penetration depth from the experimental results. Based on this finding, a more accurate relationship between the inner diameter of via holes and the diameter of in-flight droplets for different polymer thicknesses is obtained

Creep analysis of a lead-free surface mount device

In this paper finite element analysis (FEA) is used to understand the effect of a non-uniform temperature distribution on the creep and fatigue behaviour of lead-free solder joints in an electronic assembly comprising of a chip resistor mounted on printed circuit board (PCB). Solder joints in surface mount devices (SMDs) operate over a temperature range as extreme as -55degC to 125degC, which is high compared to the melting temperature of solder alloys. Exposure of solder joints to these temperatures can result in thermo-mechanical fatigue. Eutectic or near- eutectic tin-lead alloys have previously been used as an interconnection material, but the ban imposed on the use of toxic materials in electronic products demands new lead-free solder materials. This paper presents the experiments carried out using a thermal camera to obtain the real temperature distribution in the electronic assembly. These temperature distributions were used in FEA of the chip resistor under temperature cycling conditions. Unlike accelerated tests for obtaining reliability data, FEA is quick and less expensive